1. Field of the Invention
The present invention relates to an analog electronic watch, and more particularly, to a stable operation of an oscillator circuit during motor driving.
2. Description of the Related Art
In general, an analog electronic watch using a crystal oscillator circuit for use in a wristwatch or the like includes, as illustrated in FIG. 6, a crystal oscillator 60, a semiconductor device 61, a motor 62, and a cell 63. The semiconductor device 61 includes an oscillator circuit 611 capable of oscillation at a stable frequency by a combination with the external crystal oscillator 60, a frequency divider circuit 612 for frequency-dividing a reference clock signal obtained from the oscillator circuit 611 into a clock signal of a desired frequency, a constant voltage circuit 610 for driving the oscillator circuit 611 and the frequency divider circuit 612, and an output control circuit 613 for operating the motor 62.
FIG. 7 shows waveforms at nodes of the analog electronic watch circuit during operation. FIG. 7 shows the case of a negative power supply in which VDD is a ground voltage. The cell 63 and the motor 62 have resistive components, and hence, when a motor pulse is output, a cell voltage VSS drops by a voltage ΔVSS which is determined by the product of a motor load current and a cell internal resistance. When the rotation of the motor is finished to release a motor load, the cell voltage is returned to the original voltage, but the same voltage drop occurs in the next rotation of the motor. Subsequently, the voltage drop is periodically repeated. The voltage drop ΔVSS causes a transient voltage drop ΔVREG also in an output voltage VREG of the constant voltage circuit 610 for driving the oscillator circuit 611 and the frequency divider circuit 612. In order to reduce current consumption of the oscillator circuit 611 and the frequency divider circuit 612, the output voltage VREG is set as close as possible to an oscillation stop voltage VDOS of the oscillator circuit 611. When the output voltage VREG falls below the oscillation stop voltage VDOS in absolute value due to the voltage drop ΔVREG, the oscillation becomes unstable, and at worst, the oscillation stops.
To deal with this problem, the fluctuation in cell voltage is made gentle (200 μs or more) and the ratio RL/RB between a motor equivalent resistance RL and a cell internal resistance RB is set to 2 or more. Then, as shown in FIG. 8, the fluctuation at the time of the cell voltage drop becomes gentle, thus suppressing a fluctuation amount of the output voltage VREG (see, for example, Japanese Patent Application Laid-Open No. Sho 63-182591).
However, the gentleness of the fluctuation in cell voltage is determined by a time constant of the capacitance of the cell itself and the internal resistance RB. Thus, a cell having a time constant of 200 μs or less cannot be used. Further, because the ratio RL/RB between the motor equivalent resistance RL and the cell internal resistance RB needs to be set to 2 or more, a combination of the motor and the cell to be used is limited. In addition, the above-mentioned quantitative values (200 μs and RL/RB≧2 for cell fluctuation) are based on actual measurement results, but it is considered that the above-mentioned quantitative values need to be redefined depending on the difference in design value of the oscillator circuit, the difference in semiconductor manufacturing condition, and the like. Thus, the quantitative values cannot be completely defined.